I. Field of the Invention
The present invention relates to the field of dynamic memory cells utilized in integrated circuitry. More particularly, the present invention relates to a very high-density integrated circuit memory utilizing a single transistor and a single capacitor for each storage cell.
II. Description of the Prior Art
Memories based on the use of metal oxide silicon field effect transistors (MOSFETs) commonly use a single device per bit. The memory package is typically organized as a two dimensional matrix of rows and columns. The gates of a multiplicity of the MOSFETs of the cells are connected to form a row. Similarly, a column is formed by coupling the source or drain regions of the MOSFET in the memory cells. Any number of rows and columns may be constructed in this manner. Depending upon whether the source or drain is connected to the column line, the source or drain remaining is capacitively coupled to ground. As the column or, as it is often called, the data line and the source or drain region, are constructed of the same material, in the prior art they are constructed as one and the same. In a like sense, one of the capacitor plates also serves as the drain or source of the MOSFET in each memory cell. It is to be particularly noted that the performance of this storage device depends to a large part on the ratio of the capacitance of the storage device to the stray capacitance of the data line. Various prior art methods exist to increase this ratio and are discussed in U.S. Pat. No. 4,012,757 (1977).
In the field of memory, there is a constant effort to reduce the area occupied by the memory cells. This area continues to occupy the majority of a memory circuit and constitutes a limitation on the reduction of size to be achieved. It is very desirable to reduce the size of the memory cells in view of economical considerations, among other reasons. However, as the overall cell size is decreased, the ratio of cell capacitance to data line capacitance also significantly decreases, thereby affecting the overall performance of the device. Thus, the overall minimum size of a memory cell is limited by the minimum acceptable memory cell capacitance ratio. This, though, is not acceptable because the memory cells now in use in 16 K bit RAMs cannot be used in a 64 K bit RAM and still maintain the same package size. See U.S. Pat. No. 4,012,757 (1977) for a memory cell commonly used in 16 K bit Random Access Memories.
In a memory cell, the cell area is occupied by four items. These four items include the channel area of the transistor, the electrode of the capacitor, the field area isolating the cell from the other cells, and the data line. This is the structure as disclosed in U.S. Pat. No. 4,012,757. It becomes desirable to remove any one of these elements from the substrate level and thereby provide decreased area requirements. Further, the operation of the device must not be hampered, such as by decreasing the capacitance ratio.